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WIP: libs: arch: interchange: cell bel mapping implementation #1927

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WIP: libs: arch: interchange: cell bel mapping implementation #1927

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acomodi
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@acomodi acomodi commented Nov 29, 2021

Description

This PR builds on top of #1926.

The changes include:

  • Improvement of the cell to bel mapping, or in other words the mapping between a model primitive and its pb type, to allow the generation of multiple modes based on the various models that can be implemented in a pb_type
  • move the package pad bels information in the architecture reader, rather than having them in the arch structure
  • refactoring of some parts of the interchange reader, for instance by adopting the string internment to translate from an index to its string value.

Motivation and Context

Improvement in the Interchange support

How Has This Been Tested?

Tests in Catch2 framework

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

mtdudek and others added 6 commits November 29, 2021 12:06
@mtdudek @acomodi
vpr: interchange: add device data reading
8a34e73 
This PR adds basic support for the architecture reading:
  - Device
  - Layout
  - Switches

Signed-off-by: Alessandro Comodi <[email protected]>
Co-authored-by: Maciej Dudek <[email protected]>
Co-authored-by: Alessandro Comodi <[email protected]>
@acomodi
vpr: interchange: add interchange netlist reading support
c119afb 
Signed-off-by: Alessandro Comodi <[email protected]>
@acomodi
libs: arch: move common functions to util and check source files
cb085f7 
This commit also reworks the way the name is assigned to the null types

Signed-off-by: Alessandro Comodi <[email protected]>
@acomodi
libs: arch: interchange: add logical blocks and physical tile parsing
d3cb239 
Signed-off-by: Alessandro Comodi <[email protected]>
@acomodi
vpr: tests: improve interchange tests
7341abc 
Signed-off-by: Alessandro Comodi <[email protected]>
@acomodi
libs: arch: interchange: improve bel to cell mapping
c35d60d 
Signed-off-by: Alessandro Comodi <[email protected]>
@github-actions github-actions bot added libarchfpga Library for handling FPGA Architecture descriptions libvtrutil VPR VPR FPGA Placement & Routing Tool labels Nov 29, 2021
@tangxifan
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@acomodi @vaughnbetz
To follow up our discussion on placing the IO files, should we try it on the libarchfpga directory?
Since we have two readers and writers, I am thinking if we can reorganize the src directory as follows.
There will be four subdirectories, base, xml_io, interchange_io and utils

  • Thebase subdirectory contains data structures, i.e., physical_types.c|h, arch_types.h etc.
  • The xml_io subdirectory contains source files for XML reader and writer
  • The interchange_io subdirectory contains source files for FPGA interchange reader and writer
  • The utils contains any utility functions for data structure and IO reader/writers.

Let me know if this makes sense or not.

@vaughnbetz
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That seems reasonable to me.

@acomodi
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acomodi commented Dec 15, 2021

Superseded by #1937. Closing

In regards of changing the directory structure to separate files in their different scope, I think it would be better to do so after the main interchange architecture reader is in place, so that we can then open a PR which only purpose will be to change the directory structures, without affecting the source file behavior.

@acomodi acomodi closed this Dec 15, 2021
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@acomodi @tangxifan @vaughnbetz @mtdudek